The present invention relates to processes for fabricating gate insulating layers and gate insulating structures obtained by the processes, and more specifically to processes of fabricating a gate insulating structure for a charge transfer section, such as a horizontal transfer section or a vertical transfer section, of a solid state image sensor.
In the fabrication of an insulated gate structure in a horizontal or vertical transfer section of a CCD imager, a process step of thermal oxidation to form a gate oxide film is followed by a step of low-pressure CVD to deposit a silicon nitride film (Si.sub.3 N.sub.4) to improve the withstand voltage. Then, before deposition of a polysilicon electrode, this silicon nitride film is thermally oxidized to form a thin thermal oxide film under the polysilicon electrode. This step of thermal oxidation of the silicon nitride film is interposed to prevent destabilization of the flatband voltage V.sub.FV due to B-T bias in the C-V characteristic of the MOS capacitor which would result if the polysilicon gate were deposited directly on the silicon nitride film. This thermal oxide film under the polysilicon gate not only stabilizes the flatband voltage V.sub.FV, but also improves the etch selectivity relative to the underlying material in patterning the gate electrode.
In the gate insulating layer of the above-mentioned MONOS (Metal Oxide Nitride Oxide Semiconductor) structure, however, the thin oxide layer is formed under the gate electrode by the thermal oxidation of the silicon nitride layer. Therefore, this process has the following disadvantages.
First, the thermal oxidation of silicon nitride requires high temperatures and much time, so that redistribution of impurities and other adverse influences are produced specifically to the disadvantage of device miniaturization.
Second, the thermal oxidation of the silicon nitride film tends to distort the C-V characteristic of the MOS capacitor out of linearity
Third, the silicon oxide film (SiO.sub.2) on the silicon nitride layer is etched away almost completely during etching of the gate electrode. Therefore, the MOS structures formed by the first electrode layer and the second electrode layer differ from each other in the thickness of the insulating layer, and this difference causes considerable differences in capacitance and potential.
Fourth, the differences in capacitance and potential are further increased when this process is applied to a multilevel structure having three or more metallization layers. During patterning of the second electrode in the second layer, the etching process not only removes the silicon oxide film, but also attacks the underlying silicon nitride layer to such an extent as to further increase the capacitance and potential differences.
Finally, the selectivity to the underlying material becomes worse when the polysilicon gate is replaced by a tungsten silicon electrode. When a process step for covering the tungsten silicon electrode with a silicon nitride film is employed, the silicon nitride film must be thermally oxidized each time a silicon nitride layer is reformed.